GIGABIT ETHERNET CHIPSET
Figure 6. Interface Diagram
Data In
OE0
OE1
S2046/S2050
The SYNC output signal will go high whenever a
COMMA character (0011111XXX, positive running dis-
parity) is present on the parallel data outputs. The
SYNC output signal will be low at all other times. This
is true whether the S2050 is operating in 10-bit mode
or in 20-bit mode.
Lock Detect
S2046
TX/Y
Gigabit
Ethernet
Transmitter TLX/Y
RX/Y
RLX/Y
S2050
Gigabit
Ethernet
Receiver
Data Out
RCLK
LPEN
Local
Loopback
Local
Loopback
LPEN
Data Out
RCLK
S2050
Gigabit
Ethernet
Receiver
RLX/Y
RX/Y
TLX/Y
TX/Y
S2046
Gigabit
Ethernet
Transmitter
Data In
OE0, OE1
Reference Clock Input
The reference clock input must be supplied with a PECL
single-ended AC coupled crystal clock source at
±100
PPM
tolerance. See Table 3 for reference clock frequencies.
Framing
The S2050 provides SYNC character recognition and
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLKN phase will be adjusted, and the byte pre-
vious to the comma character will be lost. No glitches
will occur in the RCLKN signal due to the realign-
ment. In systems where the SYNC detect function is
undesired, a LOW on the SYNCEN input disables the
SYNC function and the data will be “unframed”.
When framing is disabled by low SYNCEN, the S2050
simply achieves bit synchronization and begins to de-
liver parallel output data words whenever it has
received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The S2050 lock detect function indicates the state of
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 2.5µs after the start of
receiving serial data inputs. If the serial data inputs
have an instantaneous phase jump (from a serial
switch, for example) the PLL will not indicate an out-
of-lock state, but will recover the correct phase
alignment. If a run length of 80-160 bits is exceeded
the loop will declare loss of lock. Input data rate varia-
tion (compared to REFCLK) can also cause loss of
lock. Table 4 shows the response of the PLL loop
circuit to input data rate variation. When lock is lost,
the PLL will attempt to reacquire bit synchronization,
and will shift from the serial input data to the refer-
ence clock so that the correct frequency downstream
clocking will be maintained.
Table 3. Receiver Operating Modes
Reference
Word
Clock RCLK/RCLKN
Data Rate Width Frequency Frequency
DWS REFSEL (Mbits/sec) (Bits)
(MHz)
(MHz)
0
1
0
1
1250.0
1250.0
20
10
62.50
125.0
62.50
62.5
Table 4. Response of PLL Loop Circuit to Input Data Rate Variation
PLL Present State
Input Data Rate
Variation (compared
to REFCLK)
0 - 244 ppm
Locked to
REFCLK
244 - 366 ppm
>366 ppm
0 - 448 ppm
Locked to
Input Data
448 - 732 ppm
>732 ppm
LOCKDETN
PLL
New State
Locked to input data
Indeterminate
Locked to REF_CLK
Locked to Input Data
Indeterminate
Locked to REF_CLK
H -->L
Indeterminate
H
L
Indeterminate
L -->H
March 29, 2000 / Revision B
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
