S2046/S2050
Figure 5. Functional Waveform
GIGABIT ETHERNET CHIPSET
S
2
0
4
6
REFCLK
(Input)
PARALLEL
DATA BUS
(Input)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10, Byte 12, Byte 14,15
11 of Data 13 of Data of Data
K28.5
Byte 16
of Data
SERIAL DATA
K28.5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
K28.5 D16
S
2
0
5
0
RCLK
(Output)
SYNC
(Output)
PARALLEL
DATA BUS
(Output)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7
of Data
Byte 8, 9
of Data
Byte 10,
Byte 12, Byte 14,15
11 of Data 13 of Data of Data
1. A.X. Widmer and P.A. Franaszek, “A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code,” IBM Research Report RC 9391,
May 1982.
S2050 RECEIVER
Architecture/Functional Description
The S2050 receiver is designed to implement the
802.3z specification receiver functions. A block dia-
gram showing the basic chip function is provided in
Figure 4.
Whenever a signal is present, the S2050 attempts to
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device’s parallel data outputs.
The S2050 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by a compatible transmitter. Clock recovery is
performed on-chip, with the output data presented to
the transmission layer as 10- or 20-bit parallel data.
The chip operates at the Gigabit Ethernet frequency
of 1250 Mbps.
Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if
the clock to be recovered is within
±100
PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLKN) is synchronized to the incoming
data stream word boundary by the detection of the
COMMA synchronization pattern (0011111XXX, positive
running disparity).
10-Bit/20-Bit Mode
The S2050 will operate with either 10-bit or 20-bit par-
allel data outputs. This option is selectable via the
DWS pin. See Tables 2 and 3. In 10-bit mode, the
10:bit data word is output on D[10:19], and D[0:9] are
driven to the logic high state.
4
March 29, 2000 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
