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S2050A 参数 Datasheet PDF下载

S2050A图片预览
型号: S2050A
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 19 页 / 158 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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S2046/S2050
S2046/S2050 OVERVIEW
The S2046 transmitter and S2050 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2050 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
The 10/20-bit parallel data handled by the S2046 and
S2050 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
characters.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 5.
A lock detect feature is provided on the receiver,
which indicates that the PLL is locked (synchronized)
to the data stream.
Loopback
GIGABIT ETHERNET CHIPSET
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
Figure 2. Interface Diagram
Parallel
Data In
TCLK
TCLKN
S2046
Transmitter
TX/Y
Serial
Data
RX/Y
S2050
Receiver
Parallel
Data Out
RCLK
RCLKN
SYNC
REFCLK
Loopback
RLX/Y
REFCLK
TLX/Y
Loopback
LOCKDETN
S2046 TRANSMITTER
Architecture/Functional Description
The S2046 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
proposed 802.3z Specification, and supports the Gi-
gabit Ethernet data rate of 1250 Mbps.
Figure 3. S2046 Functional Block Diagram
OE0
OE1
10
20
10
D
Q
10
D[19:0]
2:1
TX
TY
TEST
DWS
CONTROL
LOGIC
SHIFT
REGISTER
TLX
TLY
REFSEL
DIVIDE-BY-2
REFCLK
PLL CLOCK
MULTIPLIER
F0 = F1 X 10/20
TCLK
TCLKN
2
March 29, 2000 / Revision B