S2044/S2045
GLM COMPLIANT SERIAL INTERFACE CIRCUITS
Timing
When a 53 MHz GLM family module is in frequency
lock (either with REFCLK or a serial data stream)
RCLKN shall never have a high level duration (>2.0v)
which is less than 6.5 ns, nor a low level duration
(<0.8v) which is less than 5.8 ns (no clock shivering
shall occur). At byte realignment, RCLKN clock states
are to be extended rather than truncated). When the
GLM family module is in frequency lock (either with
REFCLK or a serial data stream) and -LCK_REF has
been inactive for at least 2500 baud times the mini-
mum instantaneous period shall always be greater
that 18.36 ns. When the PLL in the GLM is adjusting
to a new phase or a new frequency, where both the
old and new frequencies are valid Fibre Channel fre-
quencies, RCLKN shall never have a period less than
18.36 ns. In response to an input data phase jump,
the GLM shall meet the requirements of FC-PH clause
5.3 transparent to the host.
This section will detail the timing requirements of all
of the signals on the GLM interface. All timing is mea-
sured into a lumped 35pf capacitive load.
RBC[0] Timing
When -LCK_REF is pulled low, RCLKN should be in
local phase lock with TBC within 500µs. -LCK_REF,
when activated, shall stay low for a duration of at
least 500µs if receiver frequency lock is to be ex-
pected. After local phase lock has been acquired,
and when EWRAP is high, 2500 baud times after -
LCK_REF is driven high, RCLKN shall be in phase
lock with REFCLK. After local phase lock has been
acquired, and when EWRAP is low, 250 baud times
after -LCK_REF is driven high, RCLKN shall be in
phase lock with the incoming serial data stream.
RCLKN Timing Diagram
Serial Data Input Timing Table (RLX, RLY; RX, RY)
Parameters
Description
Min
Max
Units
Conditions
20% to 80%.
R
,
R
Serial data input rise and fall
—
300
ps
SDR
SDF
T
Data acquisition lock time @
<1.0625Gb/s
—
2.4
µs
LOCK
8B/10B IDLE pattern sample basis
Input data eye opening
allocation at receiver input
for BER ≤1E–12
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
(See Figure 12.)
Input Jitter
Tolerance
—
30%
bit time
For BER ≤ IE-9 see Figure 13.
17
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
