S2044/S2045
GLM COMPLIANT SERIAL INTERFACE CIRCUITS
Timing
The data on the TX[00:09] (TX[00:19]) data bus will
be sampled on every rising edge of REFCLK. The
data will be serialized and transmitted onto the serial
link if EWRAP is low and TX_SI is low. The figure
below illustrates the timing requirements of REFCLK
with respect to the TX[10:19] (TX[0:9]) signals, mini-
mum high and low durations, and the rising and falling
slew rate magnitudes. In addition, this system sup-
plied clock must not have more jitter than ±20% of a
baud interval.
REFCLK Timing Diagram
15