S2025
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
Table 3. S2025 Pin Assignment and Descriptions (continued)
Pin Name
DIN5P
DIN5N
DIN4P
DIN4N
DIN3P
DIN3N
DIN2P
DIN2N
DIN1P
DIN1N
DIN0P
DIN0N
OADDR
OACLK
IADDR
Level
Diff.
PECL
I/O
I
Pin #
14 0
141
9
8
143
142
6
7
146
145
3
5
160
181
86
Description
Differential PECL input data. Differential inputs can be used as
single-ended inputs with VBB tied to one side of each
differential input pair.
TTL
TTL
TTL
I
I
I
Serial data input to the Output Address Shift Register
Output Address Shift Register is loaded on the rising edge of
OACLK.
Serial data input to the Input Address Shift Register.
IADDR5 is the output buffer enable bit (1 = enable, 0 =
disable).
Input Address Shift Register is loaded on the rising edge of
IACLK.
Load strobe, active Low. When low, stores the configuration
data in IA register into the configuration register file.
Configuration strobe, active Low. When low, parallel loads the
contents of the configuration register file into the active
configuration latch.
Reset. Active Low. Resets all the output enable bits in the
configuration register file and in the active configuration latch.
Output data. Differential.
IACLK
LOADN
TTL
TTL
I
I
65
135
CONFIGN
TTL
I
13 9
RESETN
TTL
I
136
DOUT31P
DOUT31N
DOUT30P
DOUT30N
DOUT29P
DOUT29N
DOUT28P
DOUT28N
DOUT27P
DOUT27N
DOUT26P
DOUT26N
Diff.
PECL
O
96
94
92
93
89
91
87
90
85
83
82
80
6
June 24, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
