S2025
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
Reset Behavior
When the RESETN input pair is asserted, the S2025
assumes a configuration where all the differential out-
put drivers are disabled. Individual output drivers then
remain disabled until they are explicitly reconfigured to
be enabled.
Table 1. Data Transfer Timing
1
Symbol
tDIDO
tCFDO
tLDDO
DIMPW
FMAX
Description
Propagation delay from DIN0–31 P/N to DOUT0–31 P/N
Propagation delay from falling edge of CONFIGN to
DOUT0–31 P/N valid
Propagation delay from falling edge of LOADN to
DOUT0–31 P/N valid (When CONFIGN is held low)
Pulse width of DIN0–31 P/N
Data rate
Min.
Max.
3
6
8
Units
ns
ns
ns
ns
Mbit/s
0.650
1500
Table 2. Reconfiguration Timing
2
Symbol
t
t
t
t
t
t
t
t
t
SUIAD
HIAD
SUIAC
HIAC
SUOAD
HOAD
SUOAC
HOAC
SULC
Description
Setup time of IADDR before rising edge of IACLK
Hold time of IADDR after rising edge of IACLK
Setup time of IACLK before falling edge of LOADN
Hold time of IACLK after rising edge of LOADN
Setup time of OADDR before rising edge of OACLK
Hold time of OADDR after rising edge of OACLK
Setup time of OACLK before falling edge of LOADN
Hold time of OACLK after rising edge of LOADN
Min.
2
1
1
2
2
1
2
2
1
4.5
4.5
100
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Setup time of LOADN to CONFIGN so that the falling
edge of CONFIGN will start reconfiguration
Pulse width low of LOADN
Pulse width low of CONFIGN
IACLK, OACLK maximum frequency
LD
MPW
MPW
CF
F
1.
2.
MAX
All timing measured from the V
CC
-1.3V point on the signals.
All timing measured from the 1.5V point on the signals.
4
June 24, 1999 / Revision B
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
