欢迎访问ic37.com |
会员登录 免费注册
发布采购

S2025C-8 参数 Datasheet PDF下载

S2025C-8图片预览
型号: S2025C-8
PDF下载: 下载PDF文件 查看货源
内容描述: [Crossbar Switch, 32-Bit, CMOS, PQFP196, LDCC-196]
分类和应用: 外围集成电路
文件页数/大小: 17 页 / 126 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
 浏览型号S2025C-8的Datasheet PDF文件第2页浏览型号S2025C-8的Datasheet PDF文件第3页浏览型号S2025C-8的Datasheet PDF文件第4页浏览型号S2025C-8的Datasheet PDF文件第5页浏览型号S2025C-8的Datasheet PDF文件第6页浏览型号S2025C-8的Datasheet PDF文件第7页浏览型号S2025C-8的Datasheet PDF文件第8页浏览型号S2025C-8的Datasheet PDF文件第9页  
®
DEVICE SPECIFICATION
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
32 x 32 1.5 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
GENERAL DESCRIPTION
S2025
S2025
FEATURES
32 x 32 differential crosspoint switch
Full broadcast switching capability
Differential 10K PECL data path
Configurable differential output driver
enables
Up to 1.5 Gbit/s NRZ data rate
TTL configuration controls
Reconfigurable without disturbing operation
196-pin LDCC package
The S2025 is a very high-speed 32 x 32 differential
crosspoint switch with full broadcast capability. Any of its
32 differential PECL input signal pairs can be connected
to any or all of its 32 differential PECL output signal pairs.
In addition, the S2025 includes configurable differential
output driver enables that allow it to be expanded to
larger differential crosspoint switch structures.
The differential 10K PECL logic data path makes the
part ideal for high-speed applications. The differential
nature of the data path is retained throughout the
crosspoint structure, to minimize data distortion and to
handle NRZ data rates up to 1.5 gigabits per second.
TTL configuration controls simplify interfacing to slower
speed circuitry. Once a new configuration has been
entered into the configuration register file, the S2025
can be completely reconfigured in only 6 ns without
disturbing switch operations.
APPLICATIONS
Internet switches
Digital video
Digital demultiplexing
Microwave or fiber-optic data distribution
High-speed automatic test equipment
Datacom or telecom switching
Figure 1. Functional Block Diagram
DIN00P
DIN00N
DOUT00P
DOUT00N
DIN31P
DIN31N
PECL
Diff.
Input
Buffers
64
32 x 32
Differential
Crosspoint
64
PECL
Diff.
Output
Buffers
DOUT31P
DOUT31N
32
160
CONFIGN
OADDR
OACLK
OA
Reg
Output
Enables
Active Configuration Latch
RESETN
192
32
OADDRØ-
4
LOADN
EN
IADDRØ-
5
6
IADDR
IACLK
IA Register
DATA
5:32
Decode
SELECT
5
32 x 6
Configuration
Register File
June 24, 1999 / Revision B
1