HIPPI
S2020/S2021 SOURCE DEVICE STATE MACHINES
The detected Sequence Error will force the CONNECT
to deassert, issue one Sequence Error word on the
data outputs (SELB=4), and then return to the
{DISCON0-2} sequence with its accompanying
SELB5,6,7 sequence.
Packet or end the Connection by deasserting the RE-
QUEST signal. It should be noted that the Source may
deassert the REQUEST signal at the same time as it
deasserts the PACKET signal. In either case the S2021
returns to the SELB5,6,7 sequence (internal states
{DISCON0-2}).
In the normal data transfer procedure, the Source will
follow the asserted PACKET by asserting the BURST
signal at least one clock cycle later. If the BURST is
asserted at the same time as or before PACKET, the
Sequence Error process described above will occur.
The value in the BURST Counter is loaded into the
READY Counter, since the previous difference between
these two counters represents the READYs that were
“lost” or unanswered by the now disconnected Source.
A legally asserted and detected Burst will cause the
S2021 to place a logic 1 on the BROUT output, place
the SELB bus to state 0, and place the received data
and parity bits on the data and parity outputs as the first
word of the Burst.
Unless the Destination Host System resets the flow
counters (NRRDY set to logic 0) or resets the S2021
(Mode 0 Reset) The available Buffer count is preserved
for the next Connection.
The HIPPI Destination device Connect Control State
Machine (SM) controls the Connection state of the
HIPPI channel to which it it is attached. The Connect
Control SM has inputs from the Destination Host and
from the HIPPI channel (remote Source). Based on the
current set of inputs and the last state of this circuit the
next Connect state is entered and a related set of out-
puts is generated to the Destination Host and to the
HIPPI channel (remote Source).
The S2021 will continue to place received data and
parity on the outputs (with SELB=0) until the Source
deasserts the BURST signal. The S2021 makes no dis-
tinction between short Bursts (less than 256 words),
normal Bursts (exactly 256 words), or “extended” Bursts
(greater than 256 words). As long as the Source pro-
vides an LLRC word calculated with a modulo 256 word
count in accordance with the HIPPI Specification, the
S2021 will process the Burst without error.
The Burst is ended when the S2021 detects that the
Source has deasserted the BURST signal on the HIPPI
Channel. The data and parity word received with the
deasserted BURST are placed on the outputs as the
LLRC word (SELB=2). The received LLRC word is
compared with the LLRC internally calculated and any
mismatch will set the RLLER output to logic 1 at the
next clock cycle.
For this discussion, all external device signal names
shall be CAPITALIZED and underlined, the SM input
‘alphabet’ or decode names shall be in double quotes
(“) and all internal state names shall be
enclosed in curley brackets ‘{}’. Signals internal to the
Destination device other than previously defined state
names shall be in caret brackets ‘< >’.
CONNECT STATE MACHINE EXTERNAL
INPUTS
As each Burst is completed, the internal Burst Counter
is incremented by one as described above. During the
inter-Burst idle time the SELB bus is placed in state 3
and the general operational status word appears on the
data outputs. That status word allows the comparison
flags for the Flow Control circuit to be observed.
MSEL2-0 Mode SELect lines 2 - 0 from the Destination
Host system. Although there are eight possible
modes for the Destination device selected by these
signals, only modes 0 (RESET) and 5(OPERA-
TIONAL) are part of this discussion.
The ALLBSTS flag is 1 when the READY and BURST
counters are equal. The 64KBFRS flag is 1 when the
Last Burst and Buffer counters are equal. The
ALLRDYS flag is one when the READY and Buffer
counters are equal.
SDIC Source to Destination InterConnect signal. A ‘0’ on
this signal indicates the presence of a functioning
Source on the HIPPI channel. A ‘1’ on this signal
indicates the absence of a functioning Source on the
HIPPI channel. This signal is debounced and in-
verted to form <NRAWSDIC> (active high). A ‘1’ on
this input (or ‘0’ on the <NRAWSDIC> signal) is suffi-
cient to force the internal “DSBL” decode indepen-
dent of other inputs.
The S2021 will continue to process received Bursts un-
til the Source deasserts the PACKET signal. The inter-
Packet condition will also result in the general
operational status word appearing at the outputs (with
SELB=3).
At this point the Source may elect to start another
www.amcc.com
16
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
