Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
OTHER OPERATING MODES
JTAG TESTING
The JTAG implementation for the S2004 is compliant
with the IEEE1149.1 requirements. JTAG is used to
test the connectivity of the pins on the chip. The TAP,
(Test Access Port), provides access to the test logic of
the chip. When TRST is asserted the TAP is initialized.
TAP is a state machine that is controlled by TMS. The
test instruction and data are loaded through TDI on the
rising edge of TCK. When TMS is high the test instruc-
tion is loaded into the instruction register. When TMS
is low the test data is loaded into the data register.
TDO changes on the falling edge of TCK. All input
pins, including clocks, that have boundary scan are
observe only. They can be sampled in either normal
operational or test mode. All output pins that have
boundary scan, are observe and control. They can be
sampled as they are driven out of the chip in normal
operational mode, and they can be driven out of the
chip in test mode using the Extest instruction. Since
JTAG testing operates only on digital signals there are
some pins with analog signals that JTAG does not
cover. The JTAG implementation has the three
required instruction, Bypass, Extest, and Sample/Pre-
load.
Operating Frequency Range
The S2004 is designed to operate at serial baud rates
of .98 GHz to 1.3 GHz (800 Mbps to 1040 Mbps user
data rate). The part is specified at Fibre Channel (1062
MHz) and Gigabit Ethernet (1.25 GHz) serial baud
rates, but will operate satisfactorily at any rate in this
range. The S2204 can also operate at serial band
rates of 0.49 GHz to 0.65 GHz (400 Mbps to 520 Mbps
data rate) in the half rate operation mode.
Loopback Mode
When loopback mode is enabled, the serial data from
the transmitter is provided to the serial input of the
receiver, as shown in Figure 11. This provides the abil-
ity to perform system diagnostics and off-line testing of
the interface to verify the integrity of the serial channel.
Loopback mode is enabled independently for each
channel using its respective loopback-enable input,
LPEN.
TEST MODES
The S2004 has a testability input to aid in functional
testing of the device. The test mode is entered when
CH_LOCK is HIGH and TCLKB is HIGH. Thus users
must take care to insure that TCLKB is held LOW
when operating in the channel locked mode. The fol-
lowing conditions are asserted when in test mode:
Instruction
BYPASS
Code
11
•
REFCLK replaces the VCO CLK (it also still
goes to the transmit clock MUX).
EXTEST
00
SAMPLE/PRELOAD
ID CODE
01
•
•
TCLKA clocks all 4 transmit channels
TCLKC is MUXed in as the lock detect REF-
CLK for test purposes.
10
•
TCLKD High becomes the channel lock signal
to the whole of the chip except the transmit
clock.
JTAG Instruction Description:
The BYPASS register contains a single shift-register
stage and is used to provide a minimum-length serial
path between the TDI and TDO pins of a component
when no test operation of that component is required.
This allows more rapid movement of test data to and
from other components on a board that are required to
perform test operations.
The RESET pin is used to initialize the Transmit FIFOs
and must be asserted (LOW) prior to entering the nor-
mal operational state (see section Transmit FIFO
Initialization). Note that Reset does not disable the
TCLKO output unless the TCLKB input is HIGH.
Figure 11. S2004 Diagnostic Loopback Operation
The EXTEST instruction allows testing of off-chip cir-
cuitry and board level interconnections. Data would
typically be loaded onto the latched parallel outputs of
boundary-scan shift-register stages using the SAM-
PLE/PRELOAD instruction prior to selection of the
EXTEST instruction.
CSU
CRU
Note: Serial output data remains active during loopback opera-
tion to enable other system tests to be performed.
20
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