Revision J – April 7, 2006
S2004 – Quad Serial Backplane Device
Data Sheet
When TCLKA is the output clock source, REFCLK and
TCLKA must equal the parallel word rate (CLKSEL =
Low). Additionally, the recovered clocks and the clock
input on TCLKA must be frequency locked in order to
avoid overflow/underflow of the internal FIFOs. The
propagation delay between TCLKA and DOUTx, listed
in Table 22, shows that the phase delay between
TCLKA and the RCxP/N outputs may vary more than a
bit time based on process variation.
The recommended clocking configuration for external
clocking mode (REFCLK input clocking) is shown in
Figure 10. TCLKA is sourced from TCLKO, which is
frequency locked to the Reference clock input.
Table 8. Output Clock Mode (TMODE = 1)
Mode
CMODE
RCx P/N Freq
Half Clock Mode
0
VCO/20
Full Clock Mode
1
VCO/10
Table 9. S2004 Data Clocking
CH_LOCK
TMODE
Input Clock Source
Output Clock Source
0
0
1
1
0
1
0
1
REFCLK
TCLKx
TCLKA
RCx
REFCLK
TCLKA
TCLKA
RCA
Figure 10. External Receiver Clocking
REF
OSCILLATOR
REFCLK
TCLKO
PLL
TCLKA
Recovered
Clock
Parallel Data
2
RCxP/N
Controller/MAC
ASIC/FPGA
SerDes
AMCC Confidential and Proprietary
19
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
