QT2022/32 - Data Sheet: DS3051
Table 20: LEGACY Pin Changes to Chip Functions
Definition
Definition
LEGACY = 0
Item
Function
LEGACY = 1
1
Tx Jitter Test Pattern
Enabled by setting Register
3.2A=000Eh
Output pattern is a square wave with 8
ones and 8 zeros (00FFh)
Output pattern is a square wave with 4
ones and 4 zeros (0F0Fh)
8.2.14 Receive Equalizer Enable Control Pin (EQ_EN)
The EQ_EN pin is used to enable the fiber receive equalizer. When the pin is high, the equalizer is enabled. When
it is low, the equalizer state depends on the state of the XFP pin and the ‘override_xfp_eqn’ bit.
The control logic for the receive equalizer is shown in Table 21.
Table 21: Receive Equalizer Truth Table
‘override_xfp_eqn’
bit 1.C030h.6
Equalizer State
1 = enabled; 0 = disabled
EQ_EN Pin State
XFP Pin State
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
0
1
1
0
1
8.3 Control (Input) Pins (QT2032 only)
The pins described in this section apply to the QT2032 only. These pins are unused for the QT2022 product.
Please see Table 3 for required connectivity information.
8.3.1 LAN Mode Control Pin (LANMODE)
The LANMODE Control Pin is used to force the QT2032 into LAN mode. This pin is used in conjunction with the
MDIO “Port Type Selection” bit (address 2.7.0). When LANMODE is low, the mode is determined by the “Port Type
Selection” bit. When LANMODE is high, the mode is forced to LAN mode regardless of the state of the WIS Select
bit. The logic is summarized in Table 5.
When the LANMODE pin is high, access to the WIS register space (device 2) is disabled. MDIO writes to this
space will have no effect and MDIO reads to this space will return all 0’s.
The LANMODE pin is not defined for the QT2022.
Table 22: Application Mode Based on LANMODE Control Pin and WIS Select Bit
“Port Type Selection” bit
LANMODE Control Pin
MDIO 2.7.0
Mode
0
0
1
0
1
x
LAN
WAN
LAN
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