QT2022/32 - Data Sheet: DS3051
The following functions which are specifically for XENPAK EEPROMs are disabled in XFP mode:
•
•
•
•
•
•
EEPROM checksum
DOM capability
EEPROM_PROT protect capability
PMA/PMD type control through EEPROM
tx_flag and rx_flag for generating LASI ALARM
PMA/PMD Identifier (OUI)
Also see pin description in Table 3 on page 13.
8.2.3 Reset Control Pin (RESETN)
When the RESETN pin goes low it resets all the QT2022/32 registers to their default values. On power up, the
RESETN pin must be held low until the power supplies have reach their nominal values. While RESETN is low, all
high speed signal outputs are shut off. Once the RESETN pin goes high, the outputs will turn on (as appropriate).
Setting any of the MDIO reset registers 1.0.15, 3.0.15 and 4.0.15 to 1 will cause a soft reset. A soft reset will also
reset all registers to their default values. During a soft reset, the high speed signals are not shut off. The soft reset
is self-clearing. The reset event will occur sufficiently fast (within a few us) that no pause is required between MDIO
commands to accommodate the reset.
8.2.4 Receive LOS Control Pin (RXLOSB_I)
The RXLOSB_I input goes low to indicate a loss of optical receive signal. Driving RXLOSB_I low sets the PMA
Receive Local Fault bit in MDIO register 1.8.10, and causes MDIO register 1.10.0 (PMA Receive Signal Detected)
to go low. If Legacy = 1, driving RXLOSB_I low will also trigger PMA Receive Local Fault (1.8.10). Local Fault
ordered_sets will be output at RxXAUI when RXLOSB_I = 0.
For performing module diagnostics, the effect of the RXLOSB_I signal on the receive data path can be overridden
by setting MDIO register 1.C001h.10 to 1. When this bit is set, RXLOSB_I=0 will not cause the generation of idle
patterns at RxXAUI and will not trigger a PMA Receive Local Fault. MDIO register 1.10.0 is always controlled by
RXLOSB_I, regardless of the state of MDIO register 1.C001h.10.
The logic of the RXLOSB_I input is automatically reversed using the XFP input pin. This is required when using the
QT2022/32 in conjunction with an XFP module to match the logic of the RXLOS output from the XFP module. See
Section 8.2.2 for details.
8.2.5 Port Address Control Pins (PRTAD<4:0>)
The PRTAD bits set the port address for MDIO/C transactions. See “Management Frame Format” on page 74. for
more information on the MDIO/C interface.
8.2.6 Receive Polarity Control Pin (RXIN_SEL)
RXIN_SEL controls the 10Gb/s receive path input polarity as defined at the QT2022/32 pins/balls. The default set-
ting, RXIN_SEL=0, is compatible with XENPAK module requirements.
Table 15: RXIN Polarity
Signal
RXIN_SEL=0
RXINP
RXIN_SEL=1
RXINN
RXINN
RXINP
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