QT2022/32 - Data Sheet: DS3051
the data on the rising edge of the pin).
In “All STS-1 mode”, QT2032 will kill/gate the clock for 27 clock cycles before driving the clock for 216 (3x9x8)
clock cycles. The gap in the clock can be used for synchronization purposes. Also, the B1/B2 octets are:
In “D1-D3 mode”, QT2032 will kill/gate the clock for 219 clock cycles before driving the clock for 24 (3X8) clock
cycles. The gap in the clock can be used for synchronization purposes.
In “D4-D12 mode”, QT2032 will kill/gate the clock for 171 clock cycles before driving the clock for 72 (9X8)
clock cycles. The gap in the clock can be used for synchronization purposes.
In “D1-D12 mode”, QT2032 will kill/gate the clock for a minimum of 90 clock cycles, then drive the clock for 24
(3X8) clock cycles (D1-D3), then kill/gate the clock for a minimum of 48 clock cycles, then finally drive the clock
for 72 (9x8) clock cycles (D4-D12). The gaps in the clock can be used for synchronization purposes.
Figure 14: Serial Overhead Interface Timing Diagram
tpd = A
RXSOH_CK
RXSOH_D
…
E2bit7 E2bit8
A1bit1 A1bit2 A1bit3
…
…
th = C
tsu = B
TXSOH_CK
TXSOH_D
…
E2bit7 E2bit8
A1bit1 A1bit2 A1bit3
Table 13: Serial Overhead Interface Timing Parameters
Parameter
Value
Comment
Period
0.516μsec
243 clock cycles per frame
27 clock cycles per frame in “All STS-1 mode”
Framing Gap
Frequency
1.9375MHz
0.1μsec
A
B
C
0.1μsec
0.1μsec
7.3.9 Programmable Overhead Byte Insertion
This feature allows the insertion of 3 bytes in the WIS TX SONET frame. The insertion is limited to the transport /
path overhead, fixed stuff and the first data of the payload until column 127. The location and number of frames is
determined through 3 programmable registers, located at MDIO registers 2.C601h - 2.C603h.
The programmable control register format is shown in Figure 15. For each byte, one register is used to control
insertion the insertion mode. Two modes of insertion are available, as specified by bits 15:14 of the control register.
If continuous insertion is selected (‘11’), insertion will commence at the start of the next frame.
If a fixed number of frames is selected (‘00’, ‘01’ or ‘10’), byte insertion is initiated by a control bit located in register
bit 2.C600h.0. Once triggered, insertion will commence at the start of the next frame and will continue for the spec-
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