QT2022/32 - Data Sheet: DS3051
7.3.5 Line BIP-8 Signal Degrade (SD)
QT2032 generates a Signal Degrade (SD) alarm if the number of Line BIP-8 (B2) errors monitored during a pro-
grammable timing window (2.C400h) exceeds a programmable threshold (2.C401h). There is a second
programmable threshold (2.C402h) which is used to provide hysteresis when removing the SD alarm. The user
must specify the correct thresholds and timing window to achieve the desired BER monitoring. SD coding viola-
tions over the timing window are reported in 2.C403h, a 16 bit non-rollover counter.
At the end of each timing window, a time-out alarm is generated to notify the user that the timing window has
ended. The number of coding violations is latched to 2.C403h at the end of each window. The time-out alarm can
be programmed to trip the LASI interrupt by enabling the ‘SD Timing Window Expired Flag’ in the WIS Extended
Alarm register (MDIO register bit 2.C502h.9). The LASI interrupt can then be used by system firmware to trigger
periodic polling of the chip in order to monitor the SD error rate.
SF monitoring is enabled by setting MDIO register bit 2.C002h.7 to 1.
7.3.6 Pointer Justification Event Counters
QT2032 implements an 8 bit counter incremented by one on every Positive Stuff event. This counter does not roll-
over and is cleared to 0 on read. The Positive Stuff event counter is located in the lower 8 bits of MDIO register
2.C020h.
Likewise, the QT2032 implements an 8 bit counter incremented by one on every Negative Stuff event. This counter
does not rollover and is cleared to 0 on read. The negative Stuff event counter is located in the upper 8 bits of
MDIO register 2.C020h.
7.3.7 Extended J1 Trace Messaging (64 bytes)
The QT2032 supports both 16 and 64 byte J1 trace messaging. The IEEE 802.3 compliant 16 byte J1 trace mes-
saging is the default mode of operation. To use 64 byte J1 trace messaging, the user must enable this mode by
writing to register 2.C002h: the WIS TX will then transmit the J1 bytes located in registers 2.C200h to 2.C217h and
the WIS RX will store the received J1 bytes in registers 2.C100h to 2.C117h.
7.3.8 Transport Overhead Serial Interface
This feature allows Transport Overhead byte insertion in the WIS TX SONET frame and Transport Overhead byte
extraction from the WIS RX SONET frame. This gives the user extra flexibility to use and process SONET over-
head bytes that are not supported by the IEEE 802.3 Standard (Clause 50). This provides access to the Data
Communication Channel (DCC). This feature supports 4 modes of operation on both RX and TX:
•
insert/extract all STS-1 Transport Overhead Bytes (27 bytes per frame, corresponding to Section and Line
overhead).
•
•
•
insert/extract the D1 to D3 Bytes (3 bytes per frame).
insert/extract the D4 to D12 Bytes (9 bytes per frame).
insert/extract the D1 to D12 Bytes (12 bytes per frame).
The mode is controlled for both the Tx and Rx paths by MDIO register 2.C010h. The interface is enabled using reg-
ister bits 2.C002h.3:2.
QT2032 has a 2 wire interface on the transmit path for byte insertion: an output clock pin (TDCC_CLK) that runs at
155MHz / 80 and an input data pin (TDCC) is used to sample the incoming data (serial OH bytes). QT2032 will
sample the data at the falling edge of the clock (the external chip connected to the serial interface needs to drive a
new data value after the rising edge of the clock). Note: B1/B2 byte insertion operations are achieved using an
inversion mask, which will bitwise invert the calculated B1/B2 octets and is useful for debug purposes only. An
inserted value of all zeroes preserves the calculated B1/B2 values.
Similarly, QT2032 has a 2 wire interface on the receive path for byte extraction: an output clock pin (RDCC_CLK)
that runs at 155MHz / 80 and an output data pin (RDCC) is used to shift out the data (serial OH bytes). QT2032 will
drive a new data value on the falling edge of the clock (the chip connected to the serial interface can safely latch
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