Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 2. DCR Address Map (4KB of Device Configuration Registers)
Function
Total DCR Address Space1
Start Address
End Address
Size
1KW (4KB)1
000
3FF
By function:
Reserved
000
00C
00E
010
012
014
020
030
040
050
060
080
090
0A0
0B0
0B2
0C0
0D0
0E0
0E8
180
200
00B
00D
00F
011
013
01F
02F
03F
04F
05F
07F
08F
09F
0AF
0B1
0BF
0CF
0DF
0E7
17F
1FF
3FF
12W
2W
Clocking Power On Reset
System DCRs
Memory Controller
External Bus Controller
Reserved
2W
2W
2W
12W
16W
16W
16W
16W
32W
16W
16W
16W
2W
SRAM
L2 Controller
Memory Queue
Reserved
I2O/DMA
PLB
PLB to OPB Bridge Out
Reserved
Reserved
Reserved
14W
16W
16W
8W
Interrupt Controller 0
Interrupt Controller 1
Power Management
Reserved
152W
128W
512W
Ethernet MAL
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-
gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).
8
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