Revision 1.23 - Sept 26, 2006
Data Sheet
PowerPC 440SP Embedded Processor
Table 1. System Memory Address Map (Sheet 2 of 2)
Function
Sub Function
Start Address
End Address
Size
Reserved
PCIX0 I/O
PCIX1 I/O
PCIX2 I/O
0000 0009 0000 0000
0000 0009 0800 0000
0000 0009 1800 0000
0000 0009 2800 0000
0000 0009 07FF FFFF
0000 0009 0800 FFFF
0000 0009 1800 FFFF
0000 0009 2800 FFFF
64KB
64KB
64KB
PCIX0 Addressing Config. Regs
PCIX1 Addressing Config. Regs
PCIX2 Addressing Config. Regs
0000 0009 0EC0 0000
0000 0009 1EC0 0000
0000 0009 2EC0 0000
0000 0009 0EC0 0007
0000 0009 1EC0 0007
0000 0009 2EC0 0007
8B
8B
8B
PCIX0 Core Config. Regs
PCIX1 Core Config. Regs
PCIX2 Core Config. Regs
0000 0009 0EC8 0000
0000 0009 1EC8 0000
0000 0009 2EC8 0000
0000 0009 0EC8 0FFF
0000 0009 1EC8 0FFF
0000 0009 2EC8 0FFF
4KB
4KB
4KB
DDR PCI-X Space (HB)
PCIX0 Simple Message Passing
PCIX1 Simple Message Passing
PCIX2 Simple Message Passing
0000 0009 0EC8 1100
0000 0009 1EC8 1100
0000 0009 2EC8 1100
0000 0009 0EC8 11FF
0000 0009 1EC8 11FF
0000 0009 2EC8 11FF
256B
256B
256B
PCIX0 Special Cycle
PCIX1 Special Cycle
PCIX2 Special Cycle
Reserved
0000 0009 0ED0 0000
0000 0009 1ED0 0000
0000 0009 2ED0 0000
0000 0009 2EE0 0000
0000 0009 2F00 0000
0000 0009 FFC0 0000
0000 0009 FFE0 0000
0000 000A 0000 0000
0000 0010 0000 0000
0000 0009 0EDF FFFF
0000 0009 1EDF FFFF
0000 0009 2EDF FFFF
0000 0009 2EFF FFFF
0000 0009 FFBF FFFF
0000 0009 FFDF FFFF
0000 0009 FFFF FFFF
0000 000F FFFF FFFF
03FF FFFF FFFF FFFF
1MB
1MB
1MB
PCI Memory
3.3GB
Reserved
PCI Boot ROM (PCI Memory)
PCI Memory
2MB
24GB
Reserved4
Reserved5
0400 0010 0000 0000
0800 0000 0000 0000
07FF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF
DDR PCI-X Space (HB)
Notes:
PCI Memory
15.7EB
1. DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.
2. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating
volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.
3. When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 9 FFE0 0000 (128 KB).
4. Never decoded.
5. Unpredictable results on Read and Write operations.
6. Accessed by means of EBC Peripheral Bank Configuration Registers
AMCC Proprietary
7
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
