Revision 1.21 – June 22, 2012
PPC440GX Embedded Processor
I/O Specifications
Data Sheet
Table 12. Peripheral Interface Clock Timings
Parameter
PCIXClk input frequency (asynchronous mode)
PCIXClk period (asynchronous mode)
PCIXClk input high time
Min
Max
Units
MHz
ns
Notes
–
133.33
2
7.5
–
40% of nominal period
60% of nominal period
ns
PCIXClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
EMCTxClk input frequency MII(RMII)
EMCTxClk period MII(RMII)
EMCTxClk input high time
160
–
ns
160
–
ns
2.5(5)
40(20)
25(50)
MHz
ns
400(200)
35% of nominal period
35% of nominal period
2.5(5)
–
ns
EMCTxClk input low time
–
25(50)
400(200)
–
ns
EMCRxClk input frequency MII(RMII)
EMCRxClk period MII(RMII)
EMCRxClk input high time
EMCRxClk input low time
MHz
ns
40(20)
35% of nominal period
35% of nominal period
–
ns
–
ns
GMCRefClk input frequency
GMCRefClk period
125
MHz
ns
8
GMCRefClk input high time
GMCRefClk input low time
PerClk output frequency (for ext. master or sync. slaves)
PerClk period
47% of nominal period
47% of nominal period
33.33
53% of nominal period
53% of nominal period
83.33
ns
ns
MHz
ns
12
30
PerClk output high time
50% of nominal period
33% of nominal period
66% of nominal period
50% of nominal period
ns
PerClk output low time
ns
1000/(2TOPB1+2ns)
UARTSerClk input frequency
UARTSerClk period
–
MHz
ns
1
1
1
1
2TOPB+2
–
–
–
T
OPB+1
OPB+1
UARTSerClk input high time
UARTSerClk input low time
ns
T
ns
64
AppliedMicro Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
