Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
Signal Functional Description (Sheet 8 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Trace Interface
Description
I/O
Type
Notes
TrcBS0:2
TrcClk
Trace branch execution status.
I/O
O
3.3V LVTTL
3.3V LVTTL
Trace data capture clock, runs at 1/4 the frequency of the
processor.
Trace Execution Status is presented every fourth processor clock
cycle.
TrcES0:4
I/O
3.3V LVTTL
Additional information on trace execution and branch status.
Note:The trace signals, TrcTS0:6, are duplicated on two sets of
chip balls and are multiplexed with other signals in both
cases. This allows users to choose which set of
multiplexed signals they wish to use along with the
TrcTS0:6 signals. The trace signals in this set are primary
signals.
TrcTS0:5
(multiplexed with GPIO signals)
3.3V tolerant
2.5V CMOS
I/O
Additional information on trace execution and branch status.
TrcTS1:5
(multiplexed with EBC signals)
I/O
I/O
3.3V LVTTL
3.3V LVTTL
Note:The trace signals in this set are secondary signals.
TrcTS6
(multiplexed with EBC and
Ethernet signals)
Additional information on trace execution and branch status.
Note:This trace signal is the primary signal.
Power Pins
AGND
PLL (analog) voltage ground.
Ground.
na
na
na
na
GND
1.5V—Filtered voltages input for PLLs (analog circuits)
AxVDD
na
na
Note: A separate filter for each of the three voltages is
recommended.
OVDD
SVDD
VDD
3.3V supply—I/O (except DDR SDRAM, Ethernet)
2.5V supply—DDR SDRAM, Ethernet
1.5V supply—Logic voltage.
na
na
na
na
na
na
AMCC
57
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
