Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
GMCCrS,
GMC1TxClk,
RTBI1TxClk
Description
I/O
Type
Notes
GMII: Carrier sense
RGMII: Transmit clock
RTBI: Transmit clock
3.3V tolerant
2.5V CMOS
I/O
3.3V tolerant
2.5V CMOS
GMCRefClk
GMII, RGMII, TBI and RTBI: Gigabit reference clock
I
I
5
GMCRxD0:3,
GMC0RxD0:3,
TBIRxD0:3,
GMII: Receive data
RGMII: Receive data
TBI: Receive data
RTBI: Receive data
3.3V tolerant
2.5V CMOS
RTBI0RxD0:3
GMCRxD4:7,
GMC1RxD0:3,
TBIRxD4:7,
GMII: Receive data
RGMII: Receive data
TBI: Receive data
RTBI: Receive data
3.3V tolerant
2.5V CMOS
I
I
RTBI1RxD0:3
GMCRxDV,
GMC0RxCtl,
TBIRxD8,
GMII: Receive data valid
RGMII: Receive control
TBI: Receive data
3.3V tolerant
2.5V CMOS
RTBI0RxD4
RTBI: Receive data
GMCRxEr,
GMC1RxCtl,
TBIRxD9,
GMII: Receive error
RGMII: Receive control
TBI: Receive data
3.3V tolerant
2.5V CMOS
I/O
O
RTBI1RxD4
RTBI: Receive data
GMCTxEn,
GMC0TxCtl,
TBITxD8,
GMII: Transmit data enable
RGMII: Transmit control
TBI: Transmit data
3.3V tolerant
2.5V CMOS
RTBI0TxD4
RTBI: Transmit data
GMCTxEr,
GMC1TxCtl,
TBITxD9,
GMII: Transmit error
RGMII: Transmit control
TBI: Transmit data
3.3V tolerant
2.5V CMOS
O
6
5
RTBI1TxD4
RTBI: Transmit data
GMCTxClk
TBIRxClk1
GMII: 10/100Mbps Transmit clock
TBI: Receive clock 1
I/O
3.3V LVTTL
External Slave Peripheral Interface
Used by the PPC440GX to indicate that data transfers have
occurred.
3.3V tolerant
2.5V CMOS
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
O
I
Used by slave peripherals to indicate they are prepared to transfer
data.
3.3V tolerant
2.5V CMOS
1, 5
1, 5
3.3V tolerant
2.5V CMOS
End Of Transfer/Terminal Count.
I/O
Peripheral address bus used by PPC440GX when not in external
master mode, otherwise used by external master.
PerAddr00:31
I/O
3.3V LVTTL
1
Note: PerAddr00 is the most significant bit (msb) on this bus.
PerWBE0:3
PerBLast
External peripheral data bus byte enables.
I/O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 2
1, 4
2
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
PerCS0:7
External peripheral device select.
Peripheral data bus used by PPC440GX when not in external
master mode, otherwise used by external master.
PerData00:31
I/O
3.3V LVTTL
1
Note: PerData00 is the most significant bit (msb) on this bus.
AMCC
53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
