Revision 1.15 – August 30, 2007
440GX – Power PC 440GX Embedded Processor
Data Sheet
Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
UART1_Rx
Description
I/O
I/O
I/O
Type
Notes
1, 4
UART1 Receive data.
UART1 Transmit data.
3.3V LVTTL
3.3V LVTTL
UART1_Tx
1, 4
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
UART1_DSR/CTS
I/O
I/O
3.3V LVTTL
3.3V LVTTL
1, 4
1, 4
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
UART1_RTS/DTR
IIC Peripheral Interface
IIC0SClk
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
I/O
I/O
I/O
I/O
3.3V LVTTL
3.3V LVTTL
3.3V IIC
1, 2
1, 2
1, 2
1, 2
IIC0SDA
IIC1SClk
IIC1SDA
3.3V IIC
Interrupts Interface
IRQ00:10
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
External interrupt Requests 13 through 17.
I
I
I
3.3V LVTTL
3.3V PCI
1, 5
IRQ11:12
IRQ13:17
3.3V LVTTL
JTAG Interface
3.3V LVTTL
w/pull-up
TCK
Test Clock.
I
1
4
3.3V LVTTL
w/pull-up
TDI
Test Data In.
I
O
I
TDO
TMS
Test Data Out.
Test Mode Select.
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
5
Test Reset. During chip power-up, this signal must be low from the
start of VDD ramp-up until at least 16 SysClk cycles after VDD is
stable in order to initialize the JTAG controller.
3.3V LVTTL
w/pull-up
TRST
I
AMCC
55
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
