Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Notes:
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of
approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that
the connected device is running at precise baud rates.
2. Ethernet operation is unaffected.
3. IIC operation is unaffected.
Important: It is up to the system designer to ensure that any SSCG used with the PPC440EPx meets the above
requirements and does not adversely affect other aspects of the system.
I/O Specifications
Table 18. Peripheral Interface Clock Timings (Sheet 1 of 3)
Parameter
PCIClk frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCIClk high time
Min
Max
Units
MHz
ns
Notes
–
66.66
15
–
40% of nominal period
60% of nominal period
ns
PCIClk low time
40% of nominal period
60% of nominal period
ns
GMCMDClk frequency
GMCMDClk period
–
2.5
MHz
ns
400
–
GMCMDClk high time
160
–
ns
GMCMDClk low time
160
–
ns
GMCTxClk frequency MII
GMCTxClk period MII
2.5
25
MHz
ns
40
400
GMCTxClk high time
35% of nominal period
–
ns
GMCTxClk low time
35% of nominal period
–
ns
GMCRxClk frequency MII
GMCRxClk period MII
2.5
25
MHz
ns
40
400
GMCRxClk high time
35% of nominal period
–
ns
GMCRxClk low time
35% of nominal period
–
ns
GMCRefClk frequency
GMCRefClk period
–
125
MHz
ns
8
–
GMCRefClk high time
40% of nominal period
60% of nominal period
ns
2
2
2
2
GMCRefClk low time
40% of nominal period
60% of nominal period
ns
GMCRefClk Edge Stability (cycle-to-cycle jitter)
GMCRefClk Slew Rate
–
2
+0.15
–
ns
V/ns
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