Revision 1.31 – February 16, 2012
440EPx – PPC440EPx Embedded Processor
Data Sheet
Table 17. Clocking Specifications (continued)
Symbol
Parameter
Min
Max
Units
Notes
TC
Period
1.5
3
ns
MemClkOut and PLB Clock
FC
TC
Frequency
Period
133.33
6
166.66
7.5
MHz
ns
45% of nominal
period
55% of nominal
period
TCH
High time
ns
MAL Clock
FC
Frequency
Period
45
12
83.33
22.2
MHz
ns
TC
Note:
1. SysClk supports spread spectrum clocking with a -1% down-spread and a 40 kHz or less modulation frequency. For a 33.33MHz minimum
SysClk, the modulation frequency range of 33.00 MHz to 33.33 MHz is supported.
2. The maximum input cycle-to-cycle jitter is ± 100 ps within the frequency range 100 kHz to 20 MHz. Outside the frequency range of 100 kHz
to 20 MHz, the maximum input cycle-to-cycle jitter is ± 150 ps.
3. Slew rate is measured between 0.7V and 1.7V.
Figure 5. Timing Waveform
1.7V (2.0V)
0.7V (0.8V)
T
T
CL
CH
T
C
Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant). Slew rate should be measured between 0.7V and 1.7V.
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440EPx. This controller
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the
PPC440EPx the following conditions must be met:
• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the
PPC440EPx with one or more internal clocks at their maximum supported frequency, the SSCG can only lower
the frequency.
• The maximum frequency deviation of SysClk cannot exceed −1%, and the modulation frequency cannot
exceed 40kHz. In some cases, on-board PPC440EPx peripherals impose more stringent requirements.
74
AppliedMicro Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
