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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
External Peripheral Bus Controller (EBC)  
Features include:  
• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported  
• Up to 66.66MHz operation  
• Burst and non-burst devices  
• 16-bit byte-addressable data bus  
• 30-bit address  
• Peripheral Device pacing with external “Ready”  
• Latch data on Ready, synchronous or asynchronous  
• Programmable access timing per device  
– 256 Wait States for non-burst  
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses  
– Programmable CSon, CSoff relative to address  
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS  
• Programmable address mapping  
• External DMA Slave Support  
• External master interface  
– Write posting from external master  
– Read prefetching on PLB for external master reads  
– Bursting capable from external master  
– Allows external master access to all non-EBC PLB slaves  
– External master can control EBC slaves for own access and control  
Ethernet Controller Interface  
Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the  
chip:  
• One to two 10/100 interfaces running in full- and half-duplex modes  
– One full Media Independent Interface (MII) with 4-bit parallel data transfer  
– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer  
– Two Serial Media Independent Interfaces (SMII)  
– Packet reject support  
DMA to PLB3 Controller  
This DMA controller provides a DMA interface between the OPB and the 64-bit PLB.  
Features include:  
• Supports the following transfers:  
– Memory-to-memory transfers  
– Buffered peripheral to memory transfers  
– Buffered memory to peripheral transfers  
• Four channels  
• Scatter/Gather capability for programming multiple DMA operations  
• 32-byte buffer  
• 8-, 16-, 32-bit peripheral support (OPB and external)  
• 32-bit addressing  
• Address increment or decrement  
• Supports internal and external peripherals  
• Support for memory mapped peripherals  
• Support for peripherals running on slower frequency buses  
AMCC Proprietary  
13  
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