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PPC440EP-3JC533C 参数 Datasheet PDF下载

PPC440EP-3JC533C图片预览
型号: PPC440EP-3JC533C
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 533MHz, CMOS, PBGA456, 35 X 35 MM, ROHS COMPLIANT, PLASTIC, BGA-456]
分类和应用: 时钟外围集成电路
文件页数/大小: 87 页 / 1210 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.29 – May 07, 2008  
440EP – PPC440EP Embedded Processor  
Data Sheet  
PCI Interface  
The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is  
designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.  
Reference Specifications:  
• PowerPC CoreConnect Bus (PLB) Specification Version 3.1  
• PCI Specification Version 2.2  
• PCI Bus Power Management Interface Specification Version 1.1  
Features include:  
• PCI 2.2  
– Frequency to 66MHz  
– 32-bit bus  
• PCI Host Bus Bridge or an Adapter Device's PCI interface  
• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an  
external arbiter  
• Support for Message Signaled Interrupts  
• Simple message passing capability  
• Asynchronous to the PLB  
• PCI Power Management 1.1  
• PCI register set addressable both from on-chip processor and PCI device sides  
• Ability to boot from PCI bus memory  
• Error tracking/status  
• Supports initiation of transfer to the following address spaces:  
– Single beat I/O reads and writes  
– Single beat and burst memory reads and writes  
– Single beat configuration reads and writes (type 0 and type 1)  
– Single beat special cycles  
DDR SDRAM Memory Controller  
The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four  
256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and  
memory addressing modes are programmable.  
Features include:  
• Registered and non-registered industry standard discrete devices  
• 32-bit memory interface with optional 8-bit ECC (SEC/DED)  
• Sustainable 1.1GB/s peak bandwidth at 133MHz  
• SSTL_2 logic  
• 1 to 4 chip selects  
• CAS latencies of 2, 2.5 and 3 supported  
• DDR200/266 support  
• Page mode accesses (up to eight open pages) with configurable paging policy  
• Programmable address mapping and timing  
• Hardware and software initiated self-refresh  
• Power management (self-refresh, suspend, sleep)  
12  
AMCC Proprietary  
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