Revision 1.29 – May 07, 2008
440EP – PPC440EP Embedded Processor
Data Sheet
Table 18. Peripheral Interface Clock Timings (Continued)
Parameter
TmrClk input frequency
TmrClk period
Min
–
Max
Units
MHz
ns
Notes
100
10
–
TmrClk input high time
TmrClk input low time
Notes:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maxi-
mum OPB clock frequency is 66.66 MHz.
2. In RMII mode, a 50MHz +/- 50PPM input EMCRefClk is required. In SMII mode, a 125 MHz +/- 100PPM input EMCRefClk
is required.
Figure 6. Input Setup and Hold Waveform
Clock
1.25V
T
min
IS
T
min
IH
Inputs
Valid
Figure 7. Output Delay and Float Timing Waveform
Clock
1.25V
max
min
max
max
min
T
T
T
OV
OV
OV
T
T
min
T
OH
Outputs
OH
OH
High (Drive)
Float (High-Z)
Valid
Valid
Low (Drive)
70
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
