Revision 1.07 – September 10, 2007
PPC405EP – PowerPC 405EP Embedded Processor
On-Chip Memory (OCM)
Data Sheet
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the
processor core.
Features include:
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Low-latency access to critical instructions and data
Performance identical to cache hits without misses
Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor
and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features include:
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internal pci bus arbiter for up to three external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and can be disabled for systems which employ an external arbiter.
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PCI bus frequency up to 66MHz
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI address/data bus
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Power Management:
- PCI Bus Power Management v1.1 compliant
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
Buffering between PLB and PCI:
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- PCI target 64-byte write post buffer
- PCI target 96-byte read prefetch buffer
- PLB slave 32-byte write post buffer
- PLB slave 64-byte read prefetch buffer
Error tracking/status
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Supports PCI target side configuration
Supports processor access to all PCI address spaces:
- Single-beat PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-beat PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
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Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
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AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
