Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Data Sheet
Table 12. Peripheral Interface Clock Timings
Parameter
PerClk output frequency—133MHz
PerClk period—133MHz
Min
–
Max
Units
MHz
ns
33.33
30
–
–
PerClk output frequency—200MHz
PerClk period—200MHz
50
MHz
ns
20
–
–
PerClk output frequency—266MHz
PerClk period—266MHz
66.66
–
MHz
ns
15
PerClk output high time
45% of nominal period
45% of nominal period
55% of nominal period
55% of nominal period
± 0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
ns
1000/(2TOPB+2ns)
–
MHz
UARTSerClk input frequency (Note 1)
UARTSerClk period
2TOPB+2
TOPB+1
TOPB+1
–
–
ns
ns
UARTSerClk input high time
UARTSerClk input low time
TmrClk input frequency—133MHz
TmrClk period—133MHz
TmrClk input frequency—200MHz
TmrClk period—200MHz
TmrClk input frequency—266MHz
TmrClk period—266MHz
TmrClk input high time
–
ns
MHz
ns
–
33.33
30
–
–
50
MHz
ns
20
–
–
66.66
–
MHz
ns
15
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
TmrClk input low time
ns
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 50MHz for 200MHz parts and 66.66MHz.for 266MHz parts.
34
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
