Revision 1.02 – January 11, 2005
PPC405CR – PowerPC 405CR Embedded Processor
Pin Lists
Data Sheet
In this section there are two tables that correlate the external signals to the physical package pin (ball) on which
they appear.
The following table lists all the external signals in alphabetical order and shows the ball number on which the signal
appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate
signal in brackets. The page number listed gives the page in “Signal Functional Description” on page 23 where the
signals in the indicated interface group begin.
Table 3. Signals Listed Alphabetically (Sheet 1 of 7)
Signal Name
Ball
Interface Group
Page
AVDD
E20
Power
27
BA0
BA1
J17
SDRAM
23
23
H18
BankSel0
BankSel1
BankSel2
BankSel3
L19
N17
P17
U19
SDRAM
BusReq
CAS
P2
External Master Peripheral
SDRAM
25
23
K17
ClkEn0
ClkEn1
J19
SDRAM
23
G20
DMAAck0
DMAAck1
DMAAck2
DMAAck3
C16
B17
B16
A14
External Slave Peripheral
23
DMAReq0
DMAReq1
DMAReq2
DMAReq3
A19
C15
B15
A8
External Slave Peripheral
SDRAM
23
23
DQM0
DQM1
DQM2
DQM3
U18
W14
Y10
U8
DQMCB
V19
SDRAM
System
23
26
DrvrInh1
DrvrInh2
F17
C19
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
V17
Y18
U14
V13
Y13
V12
W11
V11
SDRAM
23
EOT0/TC0
EOT1/TC1
EOT2/TC2
EOT3/TC3
G4
F2
External Slave Peripheral
External Master Peripheral
23
25
W1
Y2
ExtAck
U5
Y3
P4
ExtReq
ExtReset
AMCC
11