Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is
selected. Refer to the PowerPC 405GPr Embedded Processor User’s Manual for more information.
5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10% and
90% points of the output voltage.
6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Output (ns)
Output Current (mA)
Signal
Clock
Notes
Setup Time Hold Time
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
(TIS min)
(TIH min)
SDRAM Interface
BA1:0
na
na
na
na
na
na
1.4
na
1.4
na
na
na
na
na
na
na
na
0
4.5
4.5
4.4
3.9
4.5
4.3
4.5
4.6
5.1
4.4
4.4
1.6
1.5
1.5
1.4
1.4
1.4
1.5
1.5
1.4
1.5
1.5
15.3
15.3
15.3
23
10.2
10.2
10.2
19.3
10.2
10.2
10.2
10.2
10.2
10.2
10.2
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
1, 2, 5
2, 5
BankSel3:0
CAS
1, 2, 5
2, 5
ClkEn0:1
DQM0:3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
2, 5
DQMCB
2, 5
ECC0:7
2, 5
MemAddr12:0
MemData0:31
RAS
na
0
1, 2, 5
2, 5
na
na
1, 2, 5
1, 2, 5
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
na
3.2
dc
na
0
6.1
na
2.2
na
2
10.3
na
7.1
na
PerClk
PerClk
PerClk
PerClk
PerClk
5
5
5
5
5
dc
0
6.4
7.1
6.5
10.3
15.3
10.3
7.1
10.2
7.1
2.2
3.3
2
0
2.3
PerCS0
PerCS1:7[GPIO10:16]
na
na
6.5
2.1
10.3
7.1
PerClk
5
PerData0:31
PerOE
4.7
na
0.9
na
0
7.2
6.5
7.2
6.6
na
1.9
2.1
2.1
2.1
na
15.3
10.3
15.3
10.3
na
10.2
7.1
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
5
5
5
5
5
5
PerPar0:3
PerR/W
2.3
3.3
5.5
2.3
10.2
7.1
0
PerReady
PerWBE0:3
0
na
0
6.1
2.2
10.3
7.1
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
na
na
na
na
0
6.1
5.9
na
6
2.2
2.1
na
1
10.3
10.3
na
7.1
7.1
na
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
SysClk
PerClk
5
5
4.1
na
5
na
na
0
15.3
10.3
na
10.2
7.1
na
5
na
6.1
na
na
0.7
na
2
5
2.1
3.1
na
na
na
-0.5
na
5
0
na
na
5
na
0
15.3
na
10.2
na
4, 5
5
PerErr
2.4
50
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
