Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
PPC405GPr New Mode Strapping Pin Assignments (Sheet 1 of 3)
Function
Option
Ball Strapping
PLL Tuning
AF3
AF2
AD16
UART0_Tx
UART0_DTR
UART0_RTS
See the PowerPC 405GPr
Embedded Processor User’s
Manual for details.
Choice 1; TUNE[9:0] = 1010111100
Choice 2; TUNE[9:0] = 0100111000
Choice 3; TUNE[9:0] = 0100110110
Choice 4; TUNE[9:0] = 0100111100
Choice 5; TUNE[9:0] = 0100111000
Choice 6; TUNE[9:0] = 1000111100
Choice 7; TUNE[9:0] = 1000111110
Choice 8; TUNE[9:0] = 1011111110
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PLL Forward Divider A 2
D16
DMAAck0
B15
DMAAck1
AC9
GPIO5[TS3]
Divide by 8
Divide by 7
Divide by 6
Divide by 5
Divide by 4
Divide by 3
Divide by 2
Divide by 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PLL Forward Divider B 2
P25
EMCTxD3
L24
EMCTxD2
AE8
GPIO6[TS4]
Divide by 8
Divide by 7
Divide by 6
Divide by 5
Divide by 4
Divide by 3
Divide by 2
Divide by 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AMCC
53
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
