Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Max
Units
MHz
ns
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
Note 1
66.66
15
Note 1
25
33.33
MHz
ns
30
40
40% of nominal period
60% of nominal period
ns
PCIClk input low time
40% of nominal period
60% of nominal period
ns
EMCMDClk output frequency
EMCMDClk period
–
2.5
MHz
ns
400
–
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
PHYTxClk period
160
–
ns
160
–
ns
2.5
25
MHz
ns
40
400
PHYTxClk input high time
35% of nominal period
–
ns
PHYTxClk input low time
35% of nominal period
–
ns
PHYRxClk input frequency
PHYRxClk period
2.5
25
MHz
ns
40
400
PHYRxClk input high time
PHYRxClk input low time
35% of nominal period
35% of nominal period
–
–
ns
–
ns
PerClk output frequency
66.66
–
MHz
ns
PerClk period
15
PerClk output high time
45% of nominal period
45% of nominal period
55% of nominal period
55% of nominal period
0.3
ns
PerClk output low time
ns
PerClk clock edge stability (phase jitter, cycle to cycle)
ns
1000/(2TOPB+2ns)
–
MHz
UARTSerClk input frequency (Note 3)
UARTSerClk period
2TOPB+2
TOPB+1
TOPB+1
–
–
ns
ns
UARTSerClk input high time
UARTSerClk input low time
TmrClk input frequency
TmrClk period
–
ns
MHz
ns
–
66.66
–
15
TmrClk input high time
TmrClk input low time
Note:
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
ns
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GPr Embedded Processor
User’s Manual for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 66.66MHz.
AMCC
45
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
