Revision 2.04 – September 7, 2007
405GPr – Power PC 405GPr Embedded Processor
Data Sheet
DC Electrical Characteristics
Parameter
Symbol
Typical
300
325
355
45
Maximum
610
Unit
mA
mA
mA
mA
mA
W
Active Operating Current (VDD)–266MHz
IDD
Active Operating Current (VDD)–333MHz
Active Operating Current (VDD)–400MHz
IDD
IDD
690
770
Active Operating Current (OVDD
PLL VDD Input current
)
IODD
IPLL
PDD
PDD
PDD
200
16
23
Active Operating Power–266MHz
Active Operating Power–333MHz
Active Operating Power–400MHz
Note:
0.72
0.76
0.82
1.92
2.07
2.23
W
W
1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are dependent on
many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD
(I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. The following
information provides details about the conditions under which the listed values were obtained:
a. In general, the values were measured using a PPC405GPr Evaluation Board with four PCI devices, an external bus master on the
peripheral bus, and external wrap-back on the Ethernet port. For all CPU clock rates, PLB = 133.3MHz, OPB = PerClk = 66.6MHz,
PCI = SysClk = 33.3MHz.
b. Typical current and power are characterized at VDD = +1.8V, OVDD = +3.3V, and TC = +36°C while running various applications
under the Linux operating system.
c. Maximum current and power are characterized at VDD = +1.9V, OVDD = +3.6V, and TC = +85°C while running applications designed
to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting SDRAM while the
internal DMA controller further increases SDRAM bus traffic.
2. AVDD should be derived from VDD using the following circuit:
L1 – 2.2μH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
AVDD
VDD
L1
+
C1 – 3.3 μF SMT tantalum
C1
C2
C3
C2 – 0.1μF SMT monolithic ceramic capacitor with X7R
AGND
dielectric or equivalent
C3 – 0.01μF SMT monolithic ceramic capacitor with X7R
GND
dielectric or equivalent
AMCC
41
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
