Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 6 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
DDR 1 (DDR2) Reference voltage 1 and 2 inputs:
SVREF1A:B
SVREF2A:B
1.25V (0.9V)
Volt ref receiver
Min. +1.15 (+0.825)V
Nom. +1.25 (+0.9)V
Max. +1.35 (0.975)V
I
Serial Communication Port (SCP) Interface
SCPClkOut
SCPDI
Output clock.
Data input.
I/O
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
SCPDO
Data output.
O
UART Peripheral Interface
The UART interface can be configured as follows:
1. One 8-pin
2. Two 4-pin
3. Two 2-pin (pull up DCD, DSR, CTS and RTS)
4. One 4-pin and one 2-pin
3.3V LVTTL
receiver
UARTSerClk
Serial clock input.
I
w/pull-up
UARTnCTS
UARTnDCD
UARTnDSR
UARTnDTR
UARTnRI
Clear to send.
I/O
I/O
I/O
I/O
I/O
I/O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 6
1, 6
1, 6
1
Data carrier detect.
Data set ready.
Data terminal ready.
Ring indicator.
1
UARTnRTS
Request to send.
1
3.3V LVTTL
receiver
w/pull-down
UARTnRx
Receive data.
Transmit data.
I
UARTnTx
O
3.3V LVTTL
USB 2.0 Interface
3.3V LVTTL
receiver
USB2Clk
USB clock.
I
5
USB2Data0:7
USB2Dir
Parallel data bus.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
Data bus direction control.
Next data byte control. When data is being transferred to the PHY,
the next byte should be sent. When data is being received from the
PHY, the next byte is available.
USB2Next
USB2Stop
I/O
I/O
3.3V LVTTL
3.3V LVTTL
Stop output control.
AMCC Proprietary
43
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
