Revision 1.09 - August 21, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 6. Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
External Peripheral Interface
PerAddr05:31
PerClk
Address bus 5:31.
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Clock output.
PerCS0
Chip selects 0.
Chip selects 1:3.
Data bus 0:31.
Data bus parity 0:3.
Output enable.
O
2
PerCS1:3
PerData00:31
PerDataPar0:3
PerOE
I/O
I/O
I/O
O
1, 2
2
3.3V LVTTL
receiver
PerReady
Slave is ready to trasfer data.
I
PerBLast
PerErr
Last transfer of burst access.
External bus error.
Read/Write.
I/O
I/O
I/O
I/O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1, 4
1, 5
1, 2
1, 2
PerRW
PerWBE0:3
ExtReset
Write Byte enable 0:3.
External reset.
External Bus Master Interface
BusReq
External bus request.
I/O
I/O
I/O
I/O
I/O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1
1
ExtAck
External data transfer complete.
External data transfer request.
External request for bus access.
External request acknowledge.
ExtReq
1, 4
1, 5
1
HoldReq
HoldAck
DMA Interface
DMAAck0:1
DMAAck2:3
DMAReq0:1
DMAReq2
DMAReq3
DMAEOT0:1
DMAEOT2:3
External peripheral DMA acknowledge.
External peripheral DMA acknowledge.
External peripheral DMA request.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1
5
External peripheral DMA request.
1, 5
5
External peripheral DMA request.
External DMA peripheral end-of-transmission.
External DMA peripheral end-of-transmission.
5
1, 5
AMCC Proprietary
41
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
