Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 10. Recommended DC Operating Conditions (Sheet 2 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
I/O Maximum Allowable Overshoot
(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)
VMAO
+3.9
V
3, 4
I/O Maximum Allowable Undershoot
(3.3V LVTTL and 2.5V/3.3 tolerant CMOS)
VMAU
TC
−0.6
−40
V
3,4
5
Case Temperature
+85
°C
Notes:
1. LPDL is least positive down level; MPUL is most positive up level.
2. Can be extended to 1.1V min., 1.2V typ., 1.3V max. with an estimated power increase of 130mW at 1.2V nom.
3. Maximum duration is 10% of the bus clock period. Bus clock is as follows:
EBC—PerClk
Ethernet—RxClk
USB—USB2Clk
4. Duration of the overshoot is time above VIH max. Duration of the undershoot is time below VIL min.
5. A 533MHz part running at 400MHz or less can operate up to a case temperature of +95°C.
Power Supply Sequence
All the PPC405EXr I/O designs are power supply sequence independent. There is no requirement that the power
supplies power up in any particular order. The following items are power sequence considerations:
• If the logic power (VDD) is applied before the I/O supply voltages, the I/Os include internal supply sequencing
circuitry that ensures the output of the receiver connected to internal chip logic is 0 until the I/O power is
applied. When the logic power supply is on and the I/O power supplies are off, the I/O logic connected to the
associated ball neither sinks or sources significant current unless influenced by an internal pull-up or pull-down
resistor. While the I/O supply is ramping, the state of the I/O balls are not predictable. This power sequence is
not destructive to the I/Os or internal logic and does not cause any functional problems.
• If the I/O power is applied before the logic power is applied, the output driver output stage (connected to the
balls) will come up in an unknown state (driving 1, driving 0, or tri-state) until the internal logic voltage is stable
within normal operating range. This power sequence is not destructive to the I/Os or internal logic and does not
cause any functional problems.
• External voltage should not be applied to the chip I/O balls before the associated I/O power supply voltage is
applied to the chip.
• A chip power down cycle must complete (all I/O supply voltages and VDD are below +0.4V) before a new
power-up cycle is started.
• During a 405EX power-up cycle, the system reset and test reset inputs should be asserted low. System reset
and test reset should remain asserted until the system clock is stable and then at least 32 system clock times
after all power supplies are stable within normal operating range. Failure to follow this reset sequence during
the power-up cycle might result in unpredictable operation.
AMCC Proprietary
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
