Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 10. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Logic Supply Voltage—333MHz & 400MHz
Logic Supply Voltage—533MHz
I/O Supply Voltage
Symbol
Minimum
+1.1
Typical
+1.15
Maximum
+1.2
Unit
V
Notes
VDD
2
VDD
OVDD
SVDD
EOVDD
+1.2
+1.25
+1.3
V
+3.15
+3.3
+3.45
V
SDRAM DDR1[2] Supply Voltage
Ethernet I/O Supply Voltage
+2.4 [+1.7]
+2.4
+2.5 [+1.8]
+2.5
+2.6 [+1.9]
+2.6
V
V
AHVDD
SAVDD
EAVDD
PLL Analog Supply Voltage
+2.4
+2.5
+2.6
V
AVDD
AVDD
VIL
Analog Supply Voltage—333MHz & 400MHz
Analog Supply Voltage—533MHz
I/O Input Low (3.3V LVTTL)
+1.1
+1.2
0
+1.15
+1.25
+1.2
+1.3
+0.8
+3.6
+0.4
+3.6
+0.7
+3.6
+0.4
+2.7
V
V
V
V
V
V
V
V
V
V
2
VIH
I/O Input High (3.3V LVTTL)
+2.0
0
VOL
VOH
VIL
I/O Output Low (3.3V LVTTL)
I/O Output High (3.3V LVTTL)
+2.4
0
I/O Input Low (3.3V tol, 2.5V CMOS)
I/O Input High (3.3V tol, 2.5V CMOS)
I/O Output Low (3.3V tol, 2.5V CMOS)
I/O Output High (3.3V tol, 2.5V CMOS)
VIH
+1.7
0
VOL
VOH
+2.0
SVREF − 0.18
VIL
VIH
I/O Input Low DDR1[2] (SSTL2)
I/O Input High DDR1[2] (SSTL2)
− 0.3
V
V
[0.125]
SVREF + 0.18
[0.125]
SVDD + 0.3
VOL
VOH
I/O Output Low DDR1[2] (SSTL2)
I/O Output High DDR1[2] (SSTL2)
See JESD8-9 (JESD8-15A) standard.
See JESD8-9 (JESD8-15A) standard.
V
V
Input Leakage Current
(no pull-up or pull-down)
IIL1
IIL2
IIL3
0
1
μA
μA
μA
Input Leakage Current
(with internal pull-down)
0 (LPDL)
200 (MPUL)
0 (MPUL)
1
1
Input Leakage Current
(with internal pull-up)
−150 (LPDL)
50
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
