Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
System Interface
3.3V tolerant
2.5V CMOS
receiver
SysClk
System input clock.
I
1
3.3V tolerant
2.5V CMOS
SysErr
Machine check exception has occurred.
O
Main system reset. This signal may be driven by the PPC405EXr to
cause a board level reset to occur.
3.3V tolerant
2.5V CMOS
SysReset
I/O
1, 2
3
3.3V LVTTL
receiver
w/pull-down
TestEn
Halt
Test enable. Reserved for manufacturing LSSD test.
External request to stop the processor.
Processor timer external input.
I
I
3.3V LVTTL
rcvr
w/pull-up
3.3V LVTTL
receiver
TmrClk
I
w/pull-up
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
GPIO00:27
GPIO29:31
I/O
3.3V LVTTL
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
3.3V tolerant
2.5V CMOS
GPIO28
I/O
O
Performance screen ring output. Use for module characterization and
screening only.
PSROUser
3
Trace Interface
TrcClk
Trace interface clock. Operates at half the CPU core frequency.
Even trace execution status.
O
3.3V LVTTL
3.3V LVTTL
TS0E
TS1E
I/O
TS0O
TS1O
Odd trace execution status.
Trace status.
I/O
I/O
3.3V LVTTL
3.3V LVTTL
TS0:3
AMCC Proprietary
43
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
