Revision 1.10 - July 10, 2008
PPC405EXr – PowerPC 405EXr Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 2 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
PCI Express Interface
PCIE0ATB
Description
I/O
Type
Notes
Analog Test Bus for manufacturing test.
na
I
Analog
CML
PCIE0ClkC
PCIE0ClkT
Differential input for external reference clock.
5
External reference resistor. Attach a 1.37 kΩ, 1% resistor between
RExt and RExtG to provide the reference for both the bias currents
and the impedance calibration circuitry.
PCIE0RExt
PCIEnRExtG
na
Analog
Differential receiver for received serial data.
PCIE0Rx
PCIE0Rx
I
LVDS receiver
LVDS driver
Note: Input must be DC coupled and biased to 0V common mode.
Differential driver for transmitted serial data.
PCIE0Tx
PCIE0Tx
O
Note: Output must be AC coupled.
Interrupts Interface
IRQ0:2
External interrupt requests.
External interrupt requests.
External interrupt requests.
External interrupt requests.
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
IRQ3:5
1
1
IRQ6
IRQ7:9
JTAG Interface
TCK
Test clock.
I
I
3.3V LVTTL
1
3.3V LVTTL
w/pull-up
TDI
Test data in.
1, 4
TDO
TMS
Test data out.
Test mode select.
O
I
3.3V LVTTL
3.3V LVTTL
w/pull-up
1
Test reset. Must be low during power-on reset to initialize the JTAG
controller and for normal operation of the chip.
3.3V LVTTL
w/pull-up
TRST
I
1, 5
42
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
