Revision 1.23 - January 28, 2009
PPC405EX – PowerPC 405EX Embedded Processor
Data Sheet
Table 19. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E)
Clock
Minimum
Maximum
Units
MHz
ns
Notes
GMCTxClk frequency
GMCTxClk high time
GMCTxClk low time
GMCRxClk frequency
GMCRxClk high time
GMCRxClk low time
GMCGTxClk
125
125
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
ns
45% of nominal
–
55% of nominal
–
ns
125
125
MHz
MHz
MHz
ns
GMCMDClk
2.5
25
GMCRefClk
125
125
GMCRefClk edge stability (phase jitter, cycle-to-cycle)
na
± 0.1
GMCRefClk rise time
GMCRefClk high time
GMCRefClk low time
GMCnRxClk
GMCnTxClk
UARTSerClk
TmrClk
na
40% of nominal
60% of nominal
125
1
ns
–
ns
–
ns
125
125
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
125
1000 / 2TOPB + 2ns
1
2
na
33
100
100
40
PerClk
TCK
na
USB2Clk (60MHz ± 0.05%)
TrcClk
57.97
66
60.03
300
Notes:
1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the PLB clock. The
maximum OPB clock frequency is 100MHz.
2. TrcClk is 1/2 CPU Clk. The maximum CPU Clk supported by instruction trace probes is 400 MHz.
56
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