Revision 1.12 - Novenber 20, 2007
PPC405EX – PowerPC 405EX Embedded Processor
Preliminary Data Sheet
Table 15. System Clocking Specifications
Symbol
Parameter
Minimum
Maximum
Units
CPU
PFC
Processor clock frequency (must be ≥SCFC)
333.33
666.66
MHz
SysClk Input
SCFC
Frequency
33.33
na
100
± 0.1
60
MHz
ns
SCTCS
SCTCH
SCTCL
SCRT
Edge stability (phase jitter, cycle-to-cycle)
High time (% of nominal period)
Low time (% of nominal period)
Rise time
40
%
40
60
%
na
0.4
ns
Other Clocks
VCOFC
VCO frequency
PLB frequency
OPB frequency
600
133
66
1800
200
MHz
MHz
MHz
PLBFC
OPBFC
100
Figure 3. Clocking Waveform
Note: SysClk and GMCRefClk are 2.5V (3.3V tolerant) signals. Rise time should be measured between 0.7V and 1.7V.
1.7 (2.0) V
1.25 (1.5) V
0.7 (0.8) V
T
T
CL
CH
T
C
52
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
