Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
DCR ADDRESS MAP
Table 2. DCR Address Map 4KB Device Configuration Register
Function
Start
End
Size
1KW (4KB)1
1
0x000
0x3FF
DCR address space
Reserved
0x000
0x010
0x012
0x014
0x080
0x090
0x092
0x0A0
0x0A8
0x0B0
0x0B8
0x0C0
0x0D0
0x0E0
0x0F0
0x100
0x140
0x180
0x200
0x280
0x300
0x00F
0x011
0x013
0x07F
0x08F
0x091
0x09F
0x0A7
0x0AF
0x0B7
0x0BF
0x0CF
0x0DF
0x0EF
0x0FF
0x13F
0x17F
0x1FF
0x27F
0x2FF
0x3FF
16W
2W
Memory controller registers
External bus controller registers
Reserved
2W
108W
16W
2W
PLB registers
Performance counters
Reserved
14W
8W
OPB bridge-out registers
Reserved
8W
Clock, control and reset
Power management
Interrupt controller 0
Interrupt controller 1
Reserved
8W
8W
16W
16W
16W
16W
64W
64W
128W
128W
128W
256W
Miscellaneous
DMA controller registers
Reserved
MAL0 registers (Ethernet)
MAL1 registers (HDLCEX)
MAL2 registers (HDLCMP)
Reserved
Notes:
1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which
equals 4 KB).
8
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