Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
PLB TO PCI BRIDGE
Data Sheet
The PLB to PCI bridge provides a mechanism for connecting PCI devices to the processor, peripherals, and mem-
ory. This interface is PCI Specification rev 2.2 compliant.
Features include:
•
Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is
optional and can be disabled for systems which employ an external arbiter.
•
PCI bus frequency up to 66MHz
- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI Address/Data Bus
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•
Power Management:
- PCI Bus Power Management v1.1 compliant
Buffering between PLB and PCI:
•
- PCI Target 64-byte write post buffer
- PCI Target 96-byte read prefetch buffer
- PLB Slave 32-byte write post buffer
- PLB Slave 64-byte read prefetch buffer
Error tracking/status
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•
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Supports PCI Target side configuration
Supports processor access to all PCI address spaces:
- Single-byte PCI I/O reads and writes
- PCI memory single-beat and prefetch-burst reads and single-beat writes
- Single-byte PCI configuration reads and writes (type 0 and type 1)
- PCI interrupt acknowledge
- PCI special cycle
•
•
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
AMCC Proprietary
DS2011
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
