Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
LIST OF FIGURES
Data Sheet
Figure 1. NPe405H Embedded Controller Functional Block Diagram ..................................................................... 6
Figure 2. 35mm, 580-Ball E-PBGA Package ......................................................................................................... 14
Figure 3. 5V-Tolerant I/O Input Current ................................................................................................................. 54
Figure 4. Clocking Waveform ................................................................................................................................. 56
Figure 5. Input Setup and Hold Waveform ............................................................................................................. 59
Figure 6. Output Delay and Float Timing Waveform .............................................................................................. 59
LIST OF TABLES
Table 1. System Address Map 4GB Total System Memory ..................................................................................... 7
Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 8
Table 3. Signals Listed Alphabetically ................................................................................................................... 15
Table 4. Signals Listed by Ball Assignment ........................................................................................................... 32
Table 5. Pin Summary ........................................................................................................................................... 41
Table 6. Signal Functional Description .................................................................................................................. 43
Table 7. Absolute Maximum Ratings ..................................................................................................................... 52
Table 8. Package Thermal Specifications .............................................................................................................. 52
Table 9. Recommended DC Operating Conditions ................................................................................................ 53
Table 10. Input Capacitance .................................................................................................................................. 54
Table 11. DC Electrical Characteristics .................................................................................................................. 55
Table 12. Clocking Specifications .......................................................................................................................... 56
Table 13. Peripheral Interface Clock Timings ........................................................................................................ 58
Table 14. I/O Specifications—All ........................................................................................................................... 60
Table 15. I/O Specifications—133 and 200MHz .................................................................................................... 62
Table 16. I/O Specifications—266MHz .................................................................................................................. 65
Table 17. Strapping Pin Assignments .................................................................................................................... 68
4
DS2011
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
