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NPE405H-3BA200C 参数 Datasheet PDF下载

NPE405H-3BA200C图片预览
型号: NPE405H-3BA200C
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerNP NPe405H嵌入式处理器 [PowerNP NPe405H Embedded Processor]
分类和应用:
文件页数/大小: 70 页 / 1343 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.01 – April 18, 2007  
NPe405H – PowerNP NPe405H Embedded Processor  
SPREAD SPECTRUM CLOCKING  
Data Sheet  
Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405H. This controller  
uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to  
as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the  
SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the  
NPe405H the following conditions must be met:  
The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the  
NPe405H with one or more internal clocks at their maximum supported frequency, the SSCG can only  
lower the frequency.  
The maximum frequency deviation cannot exceed 3%, and the modulation frequency cannot exceed  
40kHz. In some cases, on-board NPe405H peripherals impose more stringent requirements (see Note 1).  
Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock  
tracks the modulation.  
Use the SDRAM MemClkOut since it also tracks the modulation.  
Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for addi-  
tional details. This application note is available on the AMCC web site at http://www.amcc.com.  
Notes:  
1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approx-  
imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the  
connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf-  
fected by the modulation.  
2. Ethernet operation is unaffected.  
3. IIC operation is unaffected.  
4. The PCI clock specification for 66MHz allows a maximum frequency deviation of 1% at a modulation  
between 30kHz and 33kHz. PCI asynchronous mode is unaffected.  
Caution: It is up to the system designer to ensure that any SSCG used with the NPe405H meets the above  
requirements and does not adversely affect other aspects of the system.  
AMCC Proprietary  
DS2011  
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