Revision 1.01 – April 18, 2007
NPe405H – PowerNP NPe405H Embedded Processor
Data Sheet
CLOCKING SPECIFICATIONS
Table 12. Clocking Specifications
Symbol
SysClk Input
FC
Parameter
Min
Max
Units
SysClk clock input frequency
25
15
66.66
40
MHz
ns
TC
SysClk clock period
TCS
TCH
TCL
Clock edge stability (phase jitter, cycle to cycle)
Clock input high time
0.15
ns
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
ns
Clock input low time
ns
Note:Input slew rate > 2V/ns
MemClkOut Output
FC
TC
MemClkOut clock output frequency–133MHz
MemClkOut clock period–133MHz
MemClkOut clock output frequency–200MHz
MemClkOut clock period–200MHz
MemClkOut clock output frequency–266MHz
MemClkOut clock period–266MHz
Clock output high time
66.66
100
MHz
ns
15
10
FC
MHz
ns
TC
FC
133.33
MHz
ns
TC
7.5
TCH
TCL
45% of nominal period
45% of nominal period
55% of nominal period
55% of nominal period
ns
Clock output low time
ns
Other Clocks
FC
VCO frequency
400
800
66.66
100
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FC
FC
FC
FC
FC
PLB frequency–133MHz
PLB frequency–200MHz
PLB frequency–266MHz
OPB frequency–133MHz
OPB frequency–200MHz
OPB frequency–266MHz
133.33
501
50
501
FC
Notes:
1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.
CLOCKING WAVEFORM
Figure 4. Clocking Waveform
2.0V
1.5V
0.8V
T
T
CL
CH
T
C
56
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