Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Bus Protocol
PCI READ TRANSFERS
Data Sheet
When burst read transfers are attempted to the S5320
operation registers, configuration registers or expan-
sion ROM, STOP# is asserted during the first data
transfer to indicate to the initiator that no further trans-
fers (data phases) are possible. This is a target-
initiated termination where the target disconnects after
the first data phase. Figure 45 shows the signal rela-
tionships during a burst read attempt to the S5320
operation registers.
The S5320 responds to PCI bus memory or I/O read
transfers when it is selected as a target.
PCI targets may drive DEVSEL# and TRDY# after the
end of the address phase. TRDY# is not driven until
the target can provide valid data for the PCI read.
Read accesses from the S5320 operation registers
are shown in Figure 44. The S5320 conditionally
asserts STOP# in clock period 3 if the initiator keeps
FRAME# asserted during clock period 2 with IRDY#
asserted (indicating a burst is being attempted). Wait
states may be added by the initiator by not asserting
the signal IRDY# during clock 3 and beyond. If
FRAME# remains asserted, but IRDY# is not
asserted, the initiator is just adding wait states, not
necessarily attempting a burst.
For 32-bit configuration, it is recommended that the
read operation should be performed in the DWORD
boundary with the offset address increment by 4 bytes.
The starting DWORD read address should be 0, 4, 8,
C, . . . Similarly with 16-bit configuration, the starting
read WORD boundary with the offset address incre-
ment by 2 bytes. The starting WORD read address
should be 0, 2, 4, 6, . . .
PCI WRITE TRANSFERS
Figure 44. Single Data Phase PCI Bus Read of S5320
Registers or Expansion ROM
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases.
1
2
3
4
5
PCLK
Write accesses to the S5320 operation registers are
shown in Figure 46. Here, the S5320 asserts the sig-
nal STOP# in clock period 3. STOP# is asserted
because the S5320 does not support burst writes to
operation registers. Wait states may be added by the
initiator by not asserting the signal IRDY# during clock
2 and beyond. There is only one condition where
writes to S5320 internal registers do not return TRDY#
(but do assert STOP#). This is called a target-initiated
termination or target disconnect. This occurs when a
write attempt is made to a full Pass-Thru FIFO. The
assertion of STOP# without the assertion of TRDY#
indicates that the initiator should retry the operation
later. The S5320 will sustain a burst as long as the
FIFO is not full.
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
(T)
(I)
Address
Data
Bus Cmd
Byte Enables
TRDY#
DEVSEL#
STOP#
(I) Driven by Initiator
(T) Driven by Target
There are only two conditions where accesses to the
S5320 do not return TRDY#, but assert STOP#
instead. This condition is called a target-initiated termi-
nation or target disconnect. This can occur when a
read attempt is made to an empty Pass-Thru FIFO.
The second condition may occur when read accesses
to the expansion ROM generate a retry if the nvRAM
interface has not finished reading 4 bytes.
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