Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Bus Protocol
PCI BUS INTERFACE
Data Sheet
tiator-target pair. A data phase consists of at least one
PCI clock. FRAME# is deasserted to indicate that the
final data phase of a PCI cycle is occurring. Wait
states may be added to any data phase (each wait
state is one PCI clock).
This section details various events which may occur
on the S5320 PCI bus interface. Since the S5320
functions as a target or slave device, signal timing
details are given for target transactions only.
The PCI bus command presented on the C/BE[3:0]#
pins during the address phase can represent 16 possi-
ble states. Table 41 lists the PCI commands and those
which are supported by the S5320. A “Yes” in the
“Supported by S5320” column in Table 41 indicates
that the S5320 device will assert the signal DEVSEL#
when that particular command is issued along with the
appropriate PCI address.
PCI BUS TRANSACTIONS
Because the PCI bus utilizes multiplexed address/data
pins (AD[31:0]), every PCI bus transaction consists of
an address phase followed by a data phase. An
address phase is defined as the clock period in which
FRAME# transitions from inactive to active. During the
address phase, a bus command is driven by the initia-
tor on the C/BE[3:0]# signal pins. If the command
indicates a PCI read, the clock cycle following the
address phase is used to perform a “bus turn-around”
cycle. A turn-around cycle is a clock period in which
the address/data bus is not driven by an initiator or a
target device. This is used to avoid PCI bus conten-
tion. For a write command, a turn-around cycle is not
needed, and the bus goes directly from an address
phase to a data phase.
The completion or termination of a PCI cycle can be
signaled in several ways. In most cases, the comple-
tion of the final data phase is indicated by the
assertion of the ready signals from both the target
(TRDY#) and initiator (IRDY#) while FRAME# is inac-
tive. In some cases, the target is not able to continue
or support a burst transfer and will assert a STOP#
signal. This is referred to as a target disconnect. There
is also the case where an addressed device does not
exist, and the signal DEVSEL# is not driven. In this
case, the initiator is responsible for ending the cycle.
This is referred to as a master abort. The bus is
returned to the idle phase when both FRAME# and
IRDY# are deasserted.
All PCI bus transactions consist of an address phase
followed by one or more data phases. During the one-
PCI-clock-long address phase, the bus address and
command information is latched into the S5320. The
number of data phases depends on how many data
transfers are desired or are possible within a given ini-
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