Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: PCI Bus Protocol
Data Sheet
Table 41. PCI Bus Commands
C/BE[3:0]#
0000
0001
0010
0011
0100
0101
0110
0111
Command Type
Supported
No
Interrupt Acknowledge
Special Cycle
No
I/O Read
Yes
I/O Write
Yes
Reserved
No
Reserved
No
Memory Read
Memory Write
Reserved
Yes
Yes
1000
1001
1010
1011
1100
1101
1110
No
Reserved
No
Configuration Read
Configuration Write
Memory Read Multiple
Reserved
Yes
Yes
Yes 1
No
Memory Read Line
Memory Write and Invalidate
Yes 1
Yes 2
1111
1. Memory Read Multiple and Memory Read Line are executed as a Memory Read.
2. Memory Write and Invalidate is executed as a Memory Write.
cates that the next access needs to be a completely
new cycle.
PCI BURST TRANSFERS
The PCI bus, by default, expects burst transfers to be
executed. To successfully perform a burst transfer,
both the initiator and target must order their burst
address sequence in an identical fashion. There are
two different ordering schemes: linear address incre-
menting and 80486 cache line fill sequencing.
Some accesses to the S5320 controller do not support
burst transfers. For example, the S5320 does not
allow burst transfers when accesses are made to the
configuration or operation registers. Attempts to per-
form burst transfers to these regions will cause a
disconnect on the PCI bus, as described above.
Expansion ROM accesses also do not support bursts,
and will respond in the same way. Accesses to mem-
ory or I/O regions defined by the Base Address
Registers 1-4 may be bursts, if desired.
The S5320 supports only linear burst ordering.
Attempts to perform burst transfers with a scheme
other than this will cause the STOP# signal to be
asserted during the first data phase, thus issuing a dis-
connect to the initiator. The S5320 completes the initial
data phase successfully, but asserting STOP# indi-
92
DS1656
AMCC Confidential and Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
