Revision 5.03 – June 14, 2006
S5320 – PCI Match Maker: Initialization
Data Sheet
When performing a byte-wide RCR access, users
need to write the command indicating how the data is
to be used, followed by the data. These commands will
assert the internal signals LOAD_LOW_ADDR,
LOAD_HIGH_ADDR or LOAD_WR_DATA. Only one
signal is asserted at any time: once one is asserted,
the others are deasserted.
5. Write to RCR(23:16) with the high address byte.
Since signal LOAD_HIGH_ADDR is asserted, the
data
will
be
written
to
register
NVRAM_HIGH_ADDR. Note that as the nvRAM
address is limited to 11 bits, only the 3 lsbs of this
write data is actually used. As long as
LOAD_HIGH_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_HIGH_ADDR.
The final read/write interface to the external nvRAM is
via the Add-On Reset and Control Register (ARCR).
This mechanism is identical to that used for the PCI’s
RCR, except that the Add-On interface is used to
access the nvRAM via the ARCR. The latency is a bit
longer as well, due to the synchronization that must be
performed between the Add-On clock and the PCI
clock.
6. Write to RCR(31:29) = “000”, a dummy command
to deassert either LOAD_LOW_ADDR or
LOAD_HIGH_ADDR (whichever occurred last),
and to assert internal signal LOAD_WR_DATA.
This signal is used to enable the loading of the
write data register. LOAD_WR_DATA will remain
asserted until another command is issued (load
low/high address, begin read/write). As long as
LOAD_WR_DATA is asserted, a write to
RCR(23:16) will continue to overwrite the write
data register.
While on-chip arbitration logic allows simultaneous
accesses to the nvRAM via the PCI’s RCR and Add-
On’s ARCR (by queuing up the commands), there is
no logic to prevent each interface from overwriting
nvRAM contents. If an interface writes to a memory
location that the other interface has already has writ-
ten to, the value at that location will be overwritten.
7. Write to RCR(23:16) the byte to be written. Since
the signal LOAD_WR_DATA is asserted, the data
will be written to the write data register.
What follows are the sequence of steps required to
access the nvRAM via the RCR. All the scenarios
assume that the RCR is being controlled via PCI bus
transactions. By replacing RCR with ARCR in the
examples below, the operations are identical for an
Add-On device.
8. Write to RCR(31:29) = “110”, the command to
start the nvRAM write operation. This will lead to
the deassertion of LOAD_WR_DATA and will set
the busy bit, RCR(31). The nvRAM interface con-
troller will now initiate a write operation with the
external nvRAM.
The following sequence is used to perform nvRAM
writes when accessing the RCR/ARCR in a byte-
wide fashion:
9. Poll the busy bit until it is no longer set. Once
cleared, it is now safe to perform another write/
read operation to the external nvRAM. The
XFER_FAIL flag (bit 28) can be used to deter-
mine whether the transfer was successful or not.
If XFER_FAIL is asserted, this indicates that a
transfer to the nvRAM did not receive an
ACKNOWLEDGE, and the write transfer should
not be considered successful. This flag remains
set until the start of the next read/write operation.
1. Verify that busy bit, RCR(31), is not set by read-
ing RCR(31). If set, hold off starting the write
sequence (repeat step 1 until this bit clears).
2. Write to RCR(31:29) = “100”, the command to
load the low address byte. This will assert the
internal signal LOAD_LOW_ADDR, which is used
to enable the loading of the low-address register
(NVRAM_LOW_ADDR).
The busy bit will remain set until the nvRAM interface
has completed writing the data byte to the external
nvRAM, and has verified that the write sequence is fin-
ished. The nvRAM “shuts down” during a write and will
not accept any new commands (does not generate an
ACKNOWLEDGE) until it finishes the write operation.
The S5320 will continue to send commands to the
nvRAM until it responds with an ACKNOWLEDGE,
after which it clears the busy bit, indicating that the
write operation is truly complete. If the busy bit were to
be cleared after the nvRAM interface finished the
write, but before the external nvRAM was actually fin-
ished, a scenario exists where a successive write
would be ignored. In this case, the software driver
3. Write to RCR(23:16) with the low address byte.
Since signal LOAD_LOW_ADDR is asserted, the
data
will
be
written
to
register
long as
NVRAM_LOW_ADDR.
As
LOAD_LOW_ADDR is asserted, a write to
RCR(23:16) will continue to overwrite register
NVRAM_LOW_ADDR.
4. Write to RCR(31:29) = “101”, the command to
load the high address byte. This will assert the
internal signal LOAD_HIGH_ADDR, which is
used to enable the loading of the high-address
register (NVRAM_HIGH_ADDR).
84
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